Accurate Prediction of Jitter Tolerance in High-Speed Serial Links
نویسندگان
چکیده
This paper presents a novel mixed-signal verification methodology for jitter tolerance in highspeed serial-link receiver designs. The predictive approach includes identifying the jitter sources at the receiver input, generating the artificial jitter to add on input data and clock, and investigating the jitter sensitivities inside the receiver with bit error indicator. Both an artificial jitter generator and a bit error indicator are created using Verilog-AMS behavioral circuits. The simulation results show a good correlation with actual measurement data
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